IEEE

Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part I: Vertical Transistor on Gate (VTG) DRAM Cell Structure

Abstract: Two-transistor-zero-capacitor (2T0C) DRAM cell has been proposed and extensively investigated as a memory device for processing-in-memory (PIM) applications. In this two-part article, we ...
Tech Xplore

Key transistor for next-generation 3D stacked semiconductors operates without current leakage

A research team led by Professor Jae Eun Jang and Dr. Goeun Pyo from the Department of Electrical Engineering and Computer Science at DGIST has developed "dual-modulated vertically stacked transistors ...
Electronics Weekly

1nm gate-length ferroelectric transistor operates at 0.6V

Researchers at Peking University have scaled the physical gate length of a ferroelectric transistor down to 1nm and propose a novel “nanogate ultra-low-power ferroelectric transistor” architecture. By ...
IEEE

A Comprehensive Physics-Based Compact Model for CNT Thin Film Transistors—Part I: Schottky Contact

Abstract: We present a transistor model to describe the field effect current/voltage (${I}/{V}$ ) relationship in single-wall carbon nanotube thin film transistors (CNT TFTs). Based on the nature of ...