No part of a product life cycle is immune to time-to-market pressures, and that includes wafer-level parametric tests on scribe-line test structures. Parallel parametric test is emerging as a ...

Testing multiple devices in parallel using the same ATE results in reduced test time and lower costs, but it requires engineering finesse to make it so. Minimizing test measurement variation for each ...

There is considerable ongoing discussion on how to contain exponentially increasing test costs for systems-on-chip (SoCs) and microprocessors. As the transistor geometry shrinks and more transistors ...

Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and ...

SANTA ROSA, Calif.--(BUSINESS WIRE)--Keysight Technologies, Inc. (NYSE: KEYS), a leading technology company that delivers advanced design and validation solutions to help accelerate innovation to ...

According to several recent market studies, roughly 750 million cellular handsets were shipped in 2006. This quantity is likely to increase to more than one billion handsets by 2011. These numbers are ...