GitHub

cmos-logic

Designed and simulated all fundamental and universal CMOS logic gates (NOT, AND, OR, NAND, NOR, XOR, XNOR) using the Electric VLSI Design Tool. This project includes schematic design, DRC-clean ...
IEEE

An Effective Modelling of Optimized High-Speed VLSI Analog Circuit Layout using Fine-Tuned Deep Reinforcement Learning Framework

Abstract: High-speed VLSI refers to the implementation and design of very large scale integration circuits improved for fast signal processing and minimum delay, allowing them to work at higher clock ...
GitHub

VLSI-Project-5-bit-CLA

This repository contains the design and implementation of a 5-bit carry lookahead adder (CLA). It includes NGspice files for pre-layout and post-layout simulations, MAGIC files detailing the layouts ...
IEEE

A Review on Logic Gate Design and Layout Optimization in Cadence Virtuoso for Low-Power VLSI Applications

Abstract: This paper reviews logic gate design and layout optimization for low-power VLSI circuits using Cadence Virtuoso. Conventional CMOS, GDI, and MGDI logic styles are compared in terms of power, ...