Abstract: To further scale the bit-cell area of the complementary field-effect transistor (CFET) 6T static random access memory (6T-SRAM), a novel double-side cross-coupled interconnect (DSCI) ...
This article outlines the design strategies currently used to address these bottlenecks, ranging from data center systolic ...
Abstract: This paper presents an optimized 6T SRAM cell design for low-power, high-speed digital systems using advanced CMOS technology. This study aims to evaluate the performance of the proposed ...
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