He’s set himself the task of creating an entire CPU solely from NAND gates, and he’s using 74F00 chips to give a hoped-for 1MIPS performance. His design has an 8-bit data bus but a 4-bit ALU, and an ...

This directory contains Verilog HDL implementations of common digital circuits using gate-level modeling. Gate-level modeling describes digital circuits using Verilog primitive gates such as: Each ...