Hackaday

Visualizing Verilog Simulation

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some ...
Hackaday

Emulate ICs In Python

Most people who want to simulate logic ICs will use Verilog, VHDL, or System Verilog. Not [hsoft]. He wanted to use Python, and wrote a simple Python framework for doing just that. You can find the ...
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
EDN

Innologic offers hierarchical Verilog simulator

SAN JOSE, Calif. — InnoLogic Systems Inc. is calling its ESP-BV the first commercial hierarchical Verilog simulator, a binary simulator that uses the company's “hierarchical compression” technology.
Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.