SAN JOSE, CA--(Marketwire - Oct 30, 2012) - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today the tapeout of a 14-nanometer test-chip ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process ...

SAN JOSE, Calif. -- October 1, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today received three TSMC Partner of the Year Awards during ...

SAN JOSE, Calif -- Apr 8, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET ...

Cadence Design Systems announced on December 1 that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for 16nm FinFET ...

Cadence Design Systems, Inc. announced that several of its system-on-chip development tools have achieved version 0.1 of design rule manual (DRM) and SPICE model tool certification for TSMC’s ...

Today Cadence Design Systems announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing platforms. As a result of the ...

Cadence Design Systems CDNS announced that its digital and custom/analog flows had received certification on Intel's 16 FinFET process technology. Additionally, Cadence's design intellectual property ...

Companies to enable easy node-to-node migration for analog blocks with enhanced PDK across multiple FinFET processes to accelerate design closure Early customers seeing more than 2.5X design cycle ...