Nasdaq

ACM Research Highlights Availability of Portfolio of Wafer-Level Packaging Processing Equipment for OSAT Customers

Extensive Array of Back-End and Advanced Packaging Wet Wafer Process Equipment Leverages ACM’s Experience to Address Emerging Requirements for Wafer-Level Packaging FREMONT, Calif., Oct. 15, 2020 ...
Nasdaq

ACM Research Launches Its First Plating Tool to Support Wafer-Level Packaging and Plating Applications in Compound Semiconductor Manufacturing

FREMONT, Calif., Aug. 25, 2021 (GLOBE NEWSWIRE) -- ACM Research, Inc. (ACM) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging (WLP) ...
EDN

Wafer-Level Packaging Reduces Cost, Spurs Recovery

With the industry recovery coming on slowly, cost is a more important factor than ever. Semiconductor manufacturers are constantly under pressure to reduce costs, and during a down cycle they must do ...
EDN

Collision Course At The Wafer Level?

San Francisco —Competing industry teams are racing to develop wafer-level packaging (WLP) as front- and backend semiconductor manufacturing and assembly technologies converge in the advanced packaging ...

ACM Research Receives Multiple Advanced Packaging Equipment Orders from Leading Global Customers

Expands Advanced Packaging Platform Across Wafer-Level and Panel-Level Applications in Key Global Markets-FREMONT, Calif., Feb. 26, 2026 ...
Seeking Alpha

ACM Research Strengthens its Fan-Out Panel Level Packaging Portfolio with Launch of Ultra ECP ap-p Tool

FREMONT, Calif., Aug. 07, 2024 (GLOBE NEWSWIRE) -- ACM Research, Inc. (ACMR) (ACM) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging ...
Semiconductor Engineering

One Micron Damascene Redistribution for Fan-Out Wafer Level Packaging Using a Photosensitive Dielectric Material

This study investigates creation of 1.0µm RDL structures by a damascene process utilizing a photosensitive permanent dielectric material. The advantage of the photosensitive dielectric approach is ...
Digi Times

Samsung steps up fan-out wafer-level packaging deployment

Samsung Electronics has stepped up its deployment in the fan-out (FO) wafer-level packaging segment with plans to set up related production lines in Japan, according to industry sources. Samsung has ...
Digi Times

South Korea initiates major R&D project to boost chips packaging competitiveness

Recognizing the strategic importance of semiconductor packaging technology, the South Korean government is reportedly initiating a major packaging technology R&D project aimed at assisting companies ...
Semiconductor Engineering

Next Steps For Panel-Level Packaging

Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel ...
TweakTown

Apple iPhone 18 with A20 chip could switch to wafer-level multi-chip module packaging

TL;DR: Apple's iPhone 18 will feature the next-gen A20 chip using TSMC's advanced WMCM packaging with MUF technology, enhancing efficiency and yield. Eternal secured a major contract as a packaging ...