When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...

UVM (Universal Verification Methodology) is widely used in creating object-oriented test environments. UVM provides two key benefits to verification engineers; one is reusability; the other is ...

As technology becomes more integrated into our everyday life, our chips need to better communicate with the analog world. Most modern system on chip (SoC) designs therefore contain analog and ...

The first major challenge directly comes from the limited data. Unlike software engineering tasks, where large-scale public data is abundant, the hardware domain, especially UVM verification, is ...

Interface IP is an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a ...

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others ...

The advent of advanced verification methodologies such as the UVM and its predecessors VMM and OVM has changed the verification landscape in many ways. Design and verification teams used to worry ...

Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, ...