Semiconductor Engineering

SVT (Six Stacked Vertical Transistors) SRAM Cell Architecture Introduction: Design And Process Challenges Assessment

This paper presents a new design architecture for advanced logic SRAM cells using six vertical transistors (with carrier transport along the Z direction), stacked one on top of each other. Virtual ...
EDN

MoSys applies 1T-SRAM to TSMC’s 90-nm process for smallest cell yet

SUNNYVALE, Calif. — MoSys Inc. today announced it has extended its collaboration with Taiwan Semiconductor Manufacturing Co. Ltd. to include the company's one-transistor SRAM cell technology in TSMC's ...
Business Wire

SkyWater Announces Availability of SRAM Memory Compiler for 90 nm Strategic Rad Hard by Process Offering

BLOOMINGTON, Minn. & SEATTLE--(BUSINESS WIRE)--SkyWater Technology (NASDAQ: SKYT), the trusted technology realization partner, today announced a new component of its RH90 IP ecosystem to enable 90 nm ...
New Electronics

NanoIC adds advanced SRAM macros to N2 Pathfinding design kit

NanoIC, a European pilot line initiative led by imec, has released version 1.0 of its N2 Pathfinding Process Design Kit (P-PDK), introducing a major update aimed at accelerating research and design ...
New Electronics

NanoIC unveils updated Design Kit with advanced SRAM macros

The NanoIC pilot line, a European initiative led by imec to accelerate semiconductor innovation beyond the 2nm node, has announced the release of its updated N2 Pathfinding Process Design Kit (P-PDK) ...