Design-Reuse

Verilog spi slave IP Listing

The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface .
Design-Reuse

Digital Core Design Announces SPI master slave enhanced with detectors

Oct 7th, 2013 -- The DSPI_FIFO is a fully configurable SPI master/slave device, which allows to configure polarity and phase of a serial clock signal SCK. DCD’s core enables microcontroller to ...
EDN

SPI Master and Slave Functionality Implementation

This application note presents the process of implementing SPI Master and Slave functionality using the Z8 Encore! series of microcontrollers. The document provides the software implementation that ...
EDN

Enhanced Serial Peripheral Interface Master/Slave Controller

DCD-SEMI, a leading IP core provider and SoC design house based in Poland, has mastered a unique DeSPI IP Core. It is a fully configurable enhanced serial peripheral interface (eSPI) master/slave ...
Electronics Weekly

SPI FIFO can configure serial clock signal

Digital Core Design, the Poland-based IP core design house, has developed the DSPI_FIFO, a fully configurable SPI master/slave device, which allows the SoC designer to configure polarity and phase of ...