Hackaday

WheatForce: Learning From CPU Architecture Mistakes

Nothing ever made is truly perfect and indeed, CPU architectures like x86, RISC-V, ARM, and PowerPC all have their own ...
Forbes

The RISC-V Architecture Secures Smartwatches With Google And Qualcomm

Today, Google and Qualcomm announced an extension of their partnership to bring RISC-V-based systems-on-chips (SoCs) to market with support for Wear OS, a version of Android for smartwatches and ...
Morning Overview on MSN

Samsung readies PCIe 5.0 QLC SSD with a RISC-V based controller

Samsung is preparing a PCIe 5.0 SSD that pairs quad-level cell (QLC) flash memory with a RISC-V-based controller, a combination that could reshape cost and performance expectations for storage in ...
Geeky Gadgets

The future of open-source computing: How RISC-V is changing the PC industry

The RISC-V architecture is making significant strides in the PC industry, signaling a new era of innovation and competition. While its performance currently trails behind older Intel processors and ...

Hong Kong RISC-V Alliance Officially Launched to Foster Industry-Academia-Research-Investment Cross-Border Collaboration Empowering Open-Source Chip Ecosystem, Establishing an ...

The Hong Kong and China Gas Company Limited (“Towngas”), together with a number of industry-leading enterprises and institutions, announced the official launch of the Hong Kong RISC-V Alliance (HKRVA) ...
AppleInsider

Apple investigating RISC-V instruction set architecture, job listing shows

A job listing posted to Apple's website this week reveals the company is researching RISC-V instruction set architecture solutions, suggesting future in-house chip designs might implement the ...
Seeking Alpha

SensiML Expands Platform Support to Include the RISC-V Architecture

PORTLAND, Ore., Oct. 10, 2024 /PRNewswire/ -- SensiML™ Corporation, a leader in AI software for IoT and a subsidiary of QuickLogic (QUIK), today announced the integration of RISC-V® processor support ...
Blockonomi

Linea Ends Direct EVM Arithmetization, Moves to RISC-V to Match Ethereum’s Proving Roadmap

Linea, the Ethereum Layer 2 network developed by ConsenSys, is transitioning from direct EVM arithmetization to a RISC-V-based proving architecture. The team spent three years building one of the most ...
SiliconANGLE

Arm rival SiFive raises $175M to accelerate development of its alternative RISC-V chip architecture

SiFive Inc., a computer chip startup that’s developing processor technology based on the open-source RISC-V instruction set architecture, said today it has raised a hefty $175 million in a late-stage ...
Semiconductor Engineering

Differentiation And Architecture Licenses In RISC‑V

I was discussing with a colleague about the concept of architecture license in RISC-V. I realized that, in the open-source world, it can be a little tricky to grasp. In a traditional processor IP ...
Semiconductor Engineering

How To Extend The ‘Unscalable’ RISC Architectures

A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled RISC Is Fundamentally Unscalable. This blog was really quite interesting and made some very ...
Tom's Hardware on MSN

Samsung preps PCIe 5.0 QLC SSD with a controller based on open-source RISC-V architecture

The BM9K1 reportedly delivers sequential read speeds of up to 11.4 GB/s, which Samsung said is 1.6 times faster than its predecessor, the PCIe 4.0 BM9C1.