Design-Reuse

CCSDS 231.0-B-3 LDPC Encoder and Decoder IP Core from Creonic Now Available

Kaiserslautern, Germany, May 6, 2021 — Creonic GmbH, a leading IP core provider in the communications market, announced today the release of their new CCSDS 231.0-B-3 LDPC Encoder and Decoder IP cores ...
Design-Reuse

Creonic to Provide Three LDPC Decoder IP Cores for DOCSIS 3.1

Kaiserslautern, Germany, Oct. 28, 2015 - Creonic GmbH, a leading IP core supplier for communications, revealed today the availability of three IP cores for the new DOCSIS 3.1 standard. DOCSIS 3.1 ...
Nature

Dynamic Scheduling and Decoding Algorithms for LDPC and Reed-Solomon Codes

Dynamic scheduling and decoding algorithms have become pivotal in advancing the performance of error-correcting codes. Recent innovations have focused on refining Low-Density Parity-Check (LDPC) codes ...
EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
EDN

LDPC: Another Key Step Toward Shannon

For communication designers, especially those in the networking and wireless field, the Shannon limit can be seen as the Holy Grail. And, since being first defined in ...