Design-Reuse

Cadence Receives Three TSMC Partner of the Year Awards for Design IP, 16nm FinFET and 3D-IC Solutions

SAN JOSE, Calif. -- October 1, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today received three TSMC Partner of the Year Awards during ...
Business Wire

Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...
Business Wire

Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process ...
Nasdaq

Cadence (CDNS) Receives Certification for Intel 16 FinFET

Cadence Design Systems CDNS announced that its digital and custom/analog flows had received certification on Intel's 16 FinFET process technology. Additionally, Cadence's design intellectual property ...
Digi Times

HiSilicon expands adoption of Cadence tools and IP for advanced-node FinFET designs

Cadence Design Systems announced on December 1 that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for 16nm FinFET ...
Design-Reuse

GUC Tapes Out Complex 3D Stacked Die Design on Advanced FinFET Node Using Cadence Integrity 3D-IC Platform

January 10, 2024 -- Global Unichip Corporation (GUC), a leading global ASIC provider, has successfully taped out a complex 3D stacked die design on an advanced FinFET node process. The design, which ...
EDN

Cadence Unveils Broad IP Portfolio for New TSMC 16nm FinFET Plus Process

Currently under development for the 16 FF+ process, the Cadence IP portfolio includes multiple high-speed protocols for several key memory, storage and interconnect standards critical in the ...
Nasdaq

Cadence’s New Flow Automates Custom/Analog Design Migration on TSMC Advanced Technologies

Companies to enable easy node-to-node migration for analog blocks with enhanced PDK across multiple FinFET processes to accelerate design closure Early customers seeing more than 2.5X design cycle ...
EDN

Global Unichip Corporation Uses Cadence Encounter Digital Implementation System to Complete Its First Production Design on TSMC 16FF+ Process

GUC utilized the Encounter Digital Implementation System to address the implementation challenges that arise at 16FF+, including increased double-patterning and FinFET design rule checking (DRC), ...
Digi Times

Cadence, TSMC advance 7nm FinFET designs for mobile and HPC platforms

Cadence Design Systems has announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing (HPC) platforms. Save my User ...