EDN

Octasic debuts Opus2 core offering two instructions per fetch

Octasic will use the upcoming Mobile World Congress in Barcelona to debut its Opus2 DSP core, a fully asynchronous core offering dual instructions per fetch, and dedicated hardware accelerators for ...
Hackaday

Pipelining Digital Logic In FPGAs

When you first learn about digital logic, it probably seems like it is easy. You learn about AND and OR gates and figure that’s not very hard. However, going from a few basic gates to something like a ...
Design-Reuse

PP: An Application-Specific Processor for Manycore Architectures

The Protocol Processor (PP) is an application-specific processor employed in several products at Lantiq. In this paper we discuss the limitations of simple application-specific processors within ...
Design-Reuse

FPGA Implementation of DLX Microprocessor With WISHBONE SoC Bus

DLX is an open source microprocessor, it’s free and it has never been implemented in a commercial ASIC (Application Specific Integrated Circuit) design. The objective of this project is to use the ...
EDN

DSP performance tuning, part 2: Buses, DMA, and interrupts

Part 1 shows how to build a software framework, choose between cache and DMA, and partition instructions and data for optimal performance. Part 3 explains how to optimize code placement and data ...