EDN

Building an FPGA FIFO without using logic resources

Today, FPGA designers are using these flexible devices to perform everything from simple glue logic tasks to implementing complicated system on a chip (SoC) functions. The efficiency and ease of ...
TechRepublic

Verification of Asynchronous FIFO Using System Verilog

FIFO (First In First Out) is a buffer that stores data in a way that data stored first comes out of the buffer first. Asynchronous FIFO is most widely used in the System-on-Chip (SoC) designs for data ...
EDN

EDN Access–12.04.97 Multiplexers convert deep FIFO buffer to bidirectional

Interfaces to digital data recorders often require deep FIFO buffers to match the system's data rate to the recorder rate. Sometimes, a second set of FIFO buffers in the opposite direction handles ...
Semiconductor Engineering

Microarchitecture Design For Low Power

As designs move to finFET process nodes, dynamic power reduction has become a requirement. Designers have to eliminate or minimize all sources of redundant switching activity in order to reduce ...
Design-Reuse

Making SPI-4.2 Implementations More Efficient: Part 1

The SPI-4.2 interface has quickly achieved the industry-wide recognition and is highly accepted as standard high-speed interface in the networking chip space. However, creating an efficient SPI-4.2 ...